Nitrogen is our microcontroller platform for applications that demand more processing power. Like Hydrogen, it offers a simple and flexible architecture, allowing you to configure the interfaces you need while providing higher performance for more complex tasks.
Architecture
The platform features a multi-clock-domain architecture. The CPU connects to on-chip memory and the peripheral bus via a BMB interconnect with Wishbone interface. By default, the system includes a timer and a Platform-Level Interrupt Controller (PLIC) on the peripheral bus, while additional peripherals can be easily integrated as needed.
Nitrogen extends beyond basic microcontroller functionality with dedicated external memory interfaces: a HyperBUS controller for connecting high-speed HyperRAM, and an SPI XIP (eXecute In Place) interface for loading and executing code directly from external SPI Flash. This architecture enables significantly larger applications while maintaining the flexibility of the platform.
Features
Real-Time Performance
Cache-free architecture ensures predictable, deterministic execution timing. Every memory access has a known, fixed latency, making Nitrogen ideal for hard real-time systems where timing guarantees are critical.
Configurable IOs
Flexible I/O configuration allows you to customize the platform to your exact requirements. Add the peripherals you need without carrying unused hardware, optimizing both resource utilization and power consumption.
External Memory Support
Nitrogen features dedicated interfaces for external memory expansion:
- HyperBUS Interface: Connect high-speed HyperRAM for additional data storage and working memory
- SPI XIP Interface: Execute code directly from external SPI Flash without copying to RAM, enabling much larger applications
Zephyr RTOS Ready
Full support for the Zephyr Real-Time Operating System provides access to a mature, well-tested software ecosystem. Leverage thousands of device drivers, networking stacks, and application frameworks to accelerate development.
CPU Core
32-bit RISC-V CPU with a 5-stage pipeline
- Architecture: RV32IMC (Integer + Multiply/Divide + Compressed)
- Pipeline: 5-stage in-order execution
- Integer Operations: Full I extension support
- M Extension: Hardware multiply and divide
- C Extension: Compressed instructions for improved code density
- Shift Operations: Single-cycle barrel shifter
- Debug Interface: JTAG for development and testing
The RV32IM core provides efficient integer computation with hardware-accelerated multiplication and division, making it suitable for control applications, signal processing, and embedded systems that require deterministic performance.
Technical Specifications
| Component | Specification |
|---|---|
| CPU Core | 32-bit RISC-V RV32IMC, 5-stage pipeline |
| Internal Memory | Configurable on-chip SRAM |
| External Memory | HyperBUS interface (HyperRAM), SPI XIP (SPI Flash) |
| Bus Architecture | BMB interconnect with Wishbone peripheral bus |
| Clock Frequency | 25 MHz (IHP 130nm PDK) |
| Interrupt Controller | PLIC (Platform-Level Interrupt Controller) |
| Peripherals | UART, SPI, I2C, GPIO, Timer (configurable) |
| Debug | JTAG interface |
| Power Domains | Multi-clock domain architecture |
| Operating System | Zephyr RTOS support included |
| License | Open source, no license fees |
Get Started With Nitrogen
Download the IP core or contact us to discuss your project