Hydrogen is our microcontroller platform designed for real-time applications. It features a clean, streamlined architecture that lets you freely combine the inputs and outputs you need. To ensure predictable performance, Hydrogen is built without caches – delivering true real-time responsiveness.
Architecture
The platform is built as a synchronous design with a single clock domain. The CPU connects to the on-chip memory and the peripheral bus via a BMB interconnect with Wishbone interface. By default, a timer and the Platform-Level Interrupt Controller (PLIC) are always connected to this peripheral bus, and additional peripherals can be added as needed.
This simple bus architecture ensures predictable memory access, making it ideal for real-time applications.
Hydrogen includes an SPI XIP (eXecute In Place) interface, allowing code to be loaded and executed directly from external SPI Flash. This enables larger applications without requiring more on-chip memory.
Features
Real-Time Performance
Cache-free architecture ensures predictable, deterministic execution timing. Every memory access has a known, fixed latency, making Hydrogen ideal for hard real-time systems where timing guarantees are critical.
Configurable IOs
Flexible I/O configuration allows you to customize the platform to your exact requirements. Add the peripherals you need without carrying unused hardware, optimizing both resource utilization and power consumption.
External Memory Support
Nitrogen features dedicated interfaces for external memory expansion:
- SPI XIP Interface: Execute code directly from external SPI Flash without copying to RAM, enabling much larger applications
Zephyr RTOS Ready
Full support for the Zephyr Real-Time Operating System provides access to a mature, well-tested software ecosystem. Leverage thousands of device drivers, networking stacks, and application frameworks to accelerate development.
CPU Core
32-bit RISC-V CPU with a 5-stage pipeline
- Architecture: RV32IMC (Integer + Multiply/Divide + Compressed)
- Pipeline: 5-stage in-order execution
- Integer Operations: Full I extension support
- M Extension: Hardware multiply and divide
- C Extension: Compressed instructions for improved code density
- Shift Operations: Single-cycle barrel shifter
- Debug Interface: JTAG for development and testing
The RV32IM core provides efficient integer computation with hardware-accelerated multiplication and division, making it suitable for control applications, signal processing, and embedded systems that require deterministic performance.
Technical Specifications
| Component | Specification |
|---|---|
| CPU Core | 32-bit RISC-V RV32IMC, 5-stage pipeline |
| Internal Memory | Configurable on-chip SRAM |
| External Memory | SPI XIP (SPI Flash) |
| Bus Architecture | BMB interconnect with Wishbone peripheral bus |
| Clock Frequency | 25 MHz (IHP 130nm PDK) |
| Interrupt Controller | PLIC (Platform-Level Interrupt Controller) |
| Peripherals | UART, SPI, I2C, GPIO, Timer (configurable) |
| Debug | JTAG interface |
| Power Domains | Single voltage domain for simplicity |
| Operating System | Zephyr RTOS support included |
| License | Open source, no license fees |
Get Started With Hydrogen
Download the IP core or contact us to discuss your project